Computing devices may spend a majority of time in idle states. Therefore, power savings in idle states may be crucial to curb power consumption.
Some processors may allow core voltages to be adjusted depending on the activity. For example, some central processing units (CPUs) may have the capability to generate a voltage identification (VID) signal. The VID signal may indicate to the power supply unit the amount of voltage that is needed by the CPUs. A common way to supply this variable voltage may be through the use of an external voltage regulator (VR). However, an external VR may be more expensive than a fixed voltage regulator and may require bigger physical board area. In addition, an external VR may be slow in adjusting its output. As a result, external VRs may not be well suited to support dynamic power savings of CPUs over small time increments.
There exists today several on-die power saving techniques without using an external VR. These techniques include clock scaling, clock gating and power gating. Clock scaling may refer to scaling the clock frequency in accordance with work load in order to save dynamic active power. Clock gating may refer to maintaining the states of certain logic blocks of the processor when the logic blocks are not processing any data in order to eliminate switching power consumption. Although clock scaling and/or clock gating may reduce dynamic power consumption, an external VR may still be necessary to change the supply voltage in order to reduce the leakage power.
Power gating may refer to turning off power to certain logic blocks of the processor that are not currently in use to reduce the overall power leakage of a processor. Power gating may behave as an on/off control over supply voltages. Ideally, power gated logic blocks may consume no power at all. As such, power gating may be well suited to bring the logic blocks to stand-by or sleep mode. However, due to the inherent latencies associated with entering or exiting power gated states, power gating may not be tolerable under conditions of normal operation.
There is a need to save even greater amount of power, especially in circumstances when one or more power domains of a processor cannot be powered down completely, but are not processing time-sensitive data either. Furthermore, since external VRs may be costly and inefficient, it may be advantageous to have a fine-grained power delivery mechanism on the die that meets the following needs: delivery of variable voltage levels without using an external VR; Vcc tuning based on process corner to meet the product requirements; operating different logic blocks with different clock frequencies at different voltages with a common input voltage; and generating variable voltage levels from a common input voltage in order to reduce the number of platform VR rails.